Wafer-scale SOT-MRAM for analog crossbar array applications.

Code ↔ Paper

6 matches between paragraphs of the paper and lines of its authors' code, computed by the harvester (lexical-v1). Click a colored paragraph or line to see its counterpart.

The 6 matches

[1] § RESULTS AND DISCUSSION ↔ stoch_train/train_modules.py, lines 74–223 · score 0.61 · binary weight, PyTorch, Adam, gradient, single device, optimizer
[2] § RESULTS AND DISCUSSION ↔ simulator/parameters/xbar_parameters.py, lines 410–428 · score 0.58 · standard deviation, proportional devices, device conductance, generic, matching, noise
[3] § RESULTS AND DISCUSSION ↔ simulator/parameters/xbar_parameters.py, lines 410–428 · score 0.57 · conductance error, ideal devices, device conductance, deviations, matches, noise
[4] § RESULTS AND DISCUSSION ↔ applications/dnn/inference/interface/inference_net.py, lines 180–222 · score 0.56 · parasitic resistance, proportional devices, proportional noise, generic, bits, modeled
[5] § RESULTS AND DISCUSSION ↔ stoch_train/plot_varswitch_power.py, lines 220–248 · score 0.55 · switching energy, pulse length, Intersections, tail, fit, voltage
[6] § RESULTS AND DISCUSSION ↔ stoch_train/optdigits_keras/keras_infmain.py, lines 78–137 · score 0.50 · training images, 0–100 %, Adam, split, optimizer, validation

Paper

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The authors' code

Python · 453 lines · 18 KB · BSD-3-Clause · 2 matches

#
# Copyright 2017 National Technology & Engineering Solutions of Sandia, LLC
# (NTESS). Under the terms of Contract DE-NA0003525 with NTESS, the U.S. Government
# retains certain rights in this software.
#
# See LICENSE for full license details
#
from __future__ import annotations
from dataclasses import dataclass
from enum import IntEnum
from typing import Any
from .base_parameters import BaseParameters, BasePairedParameters
class ADCRangeLimits(IntEnum):
"""Defines how ADC range limits are used.
"CALIBRATED" : ADC min and max are specified manually
"MAX" : ADC limits are computed to cover the max possible range of ADC inputs,
given the size of the array
"GRANULAR" : ADC limits are computed so that the ADC level spacing is the minimum
possible separation of two ADC inputs given the target resolution of weights.
Assumes input bit slicing is used (with 1-bit DACs).
"""
CALIBRATED = 1
MAX = 2
GRANULAR = 3
@dataclass(repr=False)
class XbarParameters(BaseParameters):
"""Parameters that describe the behavior of the crossbar (xbar).
Attributes:
device (DeviceParameters): Parameters for the device used
array (ArrayParameters): Parameters for the array
adc (PairedADCParameters): Parameters for the ADC
dac (PairedDACParameters): Parameters for the DAC
Raises:
ValueError: Raised if per input bit slicing improperly configured
ValueError: Raised if gate input mode used without input bit slicing
"""
# Using field default factory to avoid isssues with declar
device: DeviceParameters = None
array: ArrayParameters = None
adc: PairedADCParameters = None
dac: PairedDACParameters = None
def validate(self) -> None:
super().validate()
if (self.adc.mvm.adc_per_ibit and not self.dac.mvm.input_bitslicing) or (
self.adc.vmm.adc_per_ibit and not self.dac.vmm.input_bitslicing
):
raise ValueError(
"ADC per input bit (adc_per_ibit) requires input bit slicing",
)
if self.array.parasitics.gate_input and not self.dac.mvm.input_bitslicing:
raise ValueError("Gate input mode can only be used with input bit slicing")
@dataclass(repr=False)
class DeviceParameters(BaseParameters):
"""Parameters that describe device behavior.
Attributes:
cell_bits (int): Programmable bit resolution of device conductance
Rmin (float): Minimum programmable resistance of the device in ohms
Rmax (float): Maximum programmable resistance of the device in ohms
infinite_on_off_ratio (bool): Whether to assume infinite conductance
On/Off ratio. If True, simulates the case of infinite Rmax.
read_noise (WeightErrorParameters): Parameters for device read noise
programming_error (WeightErrorParameters): Parameters for device
programming error
drift_error (DriftErrorParameters):# Parameters for device conductance drift
Returns:
_type_: _description_
"""
cell_bits: int = 0
Rmin: float = 1000
Rmax: float = 10000
time: int | float = 0
infinite_on_off_ratio: bool = False
clip_conductance: bool = False
read_noise: WeightErrorParameters = None
programming_error: WeightErrorParameters = None
drift_error: WeightErrorParameters = None
def validate(self) -> None:
super().validate()
# if self.cell_type is not DeviceType.NONE:
# if self.read_noise.model is not WeightErrorModel.NONE:
# self.read_noise.model = value.name
# if self.programming_error.model is not WeightErrorModel.NONE:
# self.programming_error.model = value.name
# if self.drift_error.model is not WeightErrorModel.NONE:
# self.drift_error.model = value.name
@property
def Gmin_norm(self) -> float:
# Return the minimum programmable conductance of the device, normalized
# by the maximum programmable conductance
gmin_norm = 0.0
if not self.infinite_on_off_ratio:
gmin_norm = self.Rmin / self.Rmax
return gmin_norm
@property
def Gmax_norm(self) -> float:
# Return the maximum programmable conductance normalized by itself, which is
# 1 by definition
return 1
@property
def Grange_norm(self) -> float:
# Return the difference between the max and min programmable resistance,
# normalized by the max programmable resistance
return self.Gmax_norm - self.Gmin_norm
@dataclass(repr=False)
class ArrayParameters(BaseParameters):
"""Parameters to desribe the behavior of the array.
Attributes:
Icol_max (float): Maximum current in a column, in units of the maximum current
that can be drawn by a single device in the array. Any column current that
exceeds (-Icol_max, +Icol_max) will be clipped to these bounds
parasitics (ParasiticsParameters): Parameters for array parasitics
"""
Icol_max: float = 0
parasitics: ParasiticParameters = None
# NOTE why are PairedADCParameters and PairedDACParameters separate?
@dataclass(repr=False)
class PairedADCParameters(BasePairedParameters):
"""Pairs ADC parameters for MVM and VMM operations.
Attributes:
_match (bool): Whether to sync mvm and vmm parameters
mvm (ADCParameters): ADC parameters for mvm operations
vmm (ADCParameters): VMM parameters for vmm operations
"""
_match: bool = True
mvm: ADCParameters = None
vmm: ADCParameters = None
# TODO: ADC type changer for 3.0, will be replaced in 3.1
def _change_adc_type(self):
if (
self.mvm.model == "RampADC"
or self.mvm.model == "SarADC"
or self.mvm.model == "PipelineADC"
or self.mvm.model == "CyclicADC"
):
if self.mvm.model == "RampADC":
new_mvm = RampADCParameters()
elif self.mvm.model == "SarADC":
new_mvm = SarADCParameters()
elif self.mvm.model == "PipelineADC" or self.mvm.model == "CyclicADC":
new_mvm = PipelineADCParameters()
new_mvm.update(self.mvm.as_dict())
new_mvm._parent = self
self.mvm = new_mvm
if self._match:
self.vmm = self.mvm
else:
new_mvm = ADCParameters()
for k in new_mvm.as_dict().keys():
setattr(new_mvm, k, getattr(self.mvm, k))
new_mvm._parent = self
self.mvm = new_mvm
if self._match:
self.vmm = self.mvm
if not self._match:
if (
self.vmm.model == "RampADC"
or self.vmm.model == "SarADC"
or self.vmm.model == "PipelineADC"
or self.vmm.model == "CyclicADC"
):
if self.vmm.model == "RampADC":
new_vmm = RampADCParameters()
elif self.vmm.model == "SarADC":
new_vmm = SarADCParameters()
elif self.vmm.model == "PipelineADC" or self.vmm.model == "CyclicADC":
new_vmm = PipelineADCParameters()
new_vmm.update(self.vmm.as_dict())
new_vmm._parent = self
self.vmm = new_vmm
else:
new_vmm = ADCParameters()
for k in new_vmm.as_dict().keys():
setattr(new_vmm, k, getattr(self.vmm, k))
new_vmm._parent = self
self.vmm = new_vmm
@dataclass(repr=False)
class PairedDACParameters(BasePairedParameters):
"""Pairs DAC parameters for MVM and VMM operations.
Attributes:
_match (bool): Whether to sync mvm and vmm parameters
mvm (DACParameters): DAC parameters for mvm operations
vmm (DACParameters): VMM parameters for vmm operations
"""
_match: bool = True
mvm: DACParameters = None
vmm: DACParameters = None
@dataclass(repr=False)
class ADCParameters(BaseParameters):
"""Parameters for the behavior of the analog-to-digital converter used to digitize
the analog MVM/VMM outputs from the array.
Attributes:
model (str): name of the ADC model. This must match the name of a child class
of IADC, other than "ADC"
bits (int): bit resolution of the ADC digital output
stochastic_rounding (bool): whether to probabilistically round an ADC input
value to one of its two adjacent ADC levels, with a probability set by the
distance to the level. If False, value is always rounded to the closer
level.
adc_per_ibit (bool): whether to digitize the MVM result of each input bit
slice. This is only used if input_bitslicing = True in the associated
DACParameters. If False, it is assumed by shift-and-add accumulation of
input bits is done using analog peripheral circuits and only the final
result is digitized.
calibrated_range (list): the manually specified ADC min and max. This is only
used if adc_range_option = ADCRangeLimits.CALIBRATED. If not using BITSLICED
core, this must be a 1D array of length 2. If using BITSLICED core, this
must be a 2D array with shape (num_slices, 2) that stores the ADC min/max
for each bit slice of the core.
adc_range_option (ADCRangeLimits): Which method is used to set ADC range limits
Raises:
ValueError: Raised if granular ADC is enabled with incompatible options
"""
model: str = "IdealADC"
bits: int = 0
signed: bool = True
stochastic_rounding: bool = False
adc_per_ibit: bool = False
calibrated_range: list = None
adc_range_option: ADCRangeLimits = ADCRangeLimits.CALIBRATED
# TODO: Quick little hack for swapping param objects, just till 3.1 changes
def __setattr__(self, name: str, value: Any) -> None:
super().__setattr__(name, value)
if name == "model":
if self.parent is not self:
self.parent._change_adc_type()
def validate(self) -> None:
super().validate()
if self.adc_range_option is ADCRangeLimits.GRANULAR and not self.adc_per_ibit:
raise ValueError(
"Granular ADC range is only supported for digital input"
"shift and add (adc_per_ibit)",
)
# TODO: Temporary for 3.0
@classmethod
def get_adc_type(cls, model: str):
if model == "RampADC":
return RampADCParameters
elif model == "SarADC":
return SarADCParameters
elif model == "PipelineADC" or model == "CyclicADC":
return PipelineADCParameters
else:
return ADCParameters
@dataclass(repr=False)
class RampADCParameters(ADCParameters):
"""Ramp ADC specific non-ideality parameters.
Attributes:
gain_db (float): Open-loop gain in decibels of the operational amplifier at the
output of the capacitive DAC (CDAC) used to generate the voltage ramp
sigma_capacitor (float): Standard deviation of the random variability in the
minimum-sized capacitor in the CDAC, normalized by the minimum capacitance
value.
sigma_comparator (float): Standard deviation of the random variability in the
input offset voltage of the comparator used for ramp comparison. There is a
comparator associated with every array column (MVM) and/or row (VMM). The
offset is normalized by the reference voltage used for the ramp.
symmetric_cdac (bool): Whether to use the symmetric CDAC design that treats the
ADC levels as two's complement signed integers. If False, uses an
alternative CDAC design that treats the ADC levels as unsigned integers.
"""
gain_db: float = 100
sigma_capacitor: float = 0.0
sigma_comparator: float = 0.0
symmetric_cdac: bool = True
@dataclass(repr=False)
class SarADCParameters(ADCParameters):
"""SAR ADC specific non-ideality parameters.
Attributes:
gain_db (float): Open-loop gain in decibels of the operational amplifier at the
output of the capacitive DAC (CDAC)
sigma_capacitor (float): Standard deviation of the random variability in the
minimum-sized capacitor in the CDAC, normalized by the minimum capacitance
value.
sigma_comparator (float): Standard deviation of the random variability in the
input offset voltage of the comparator. The comparator compares the analog
ADC input to the analog CDAC output during each SAR cycle. There is a
comparator for every group of ADC inputs.
split_cdac (bool): Whether to use the split capacitor CDAC design to reduce the
average size of the capacitor in the CDAC.
group_size (int): Number of ADC inputs that share a SAR unit. Inputs within a
group use the same CDAC and comparator. This corresponds to the number of
grouped columns (MVM) or grouped rows (VMM) of the array.
"""
gain_db: float = 100
sigma_capacitor: float = 0.0
sigma_comparator: float = 0.0
split_cdac: bool = True
group_size: int = 8
@dataclass(repr=False)
class PipelineADCParameters(ADCParameters):
"""Pipeline/Cycli ADC specific non-ideality parameters.
Attributes:
gain_db (float): Open-loop gain in decibels of the operational amplifier used as
the residue amplifier in a 1.5-bit stage of the pipeline ADC.
sigma_C1 (float): Standard deviation of the random variability in capacitor C1
used to amplify the voltage by 2X in the 1.5-bit switched-capacitor stage.
The amplification factor is (1 + C1/C2), where C1 = C2 in the ideal case.
sigma_C2 (float): Standard deviation of the random variability in capacitor C2
in the 1.5-bit ADC stage, normalized by the nominal value of C2.
sigma_Cpar (float): Standard deviation of the random variability in the
parasitic capacitance at the negative input of the operational amplifier in
the 1.5-bit stage, normalized by the nominal value of C1.
sigma_comparator (float): Standard deviation of the random variability in the
input offset voltage of the comparators used in the 1.5-bit stages.
group_size (int): Number of ADC inputs that share single pipeline ADC and its
random capacitor mismatches and comparator offsets. This corresponds to the
number of grouped columns (MVM) or grouped rows (VMM) of the array.
"""
gain_db: float = 100
sigma_C1: float = 0.0
sigma_C2: float = 0.0
sigma_Cpar: float = 0.0
sigma_comparator: float = 0.0
group_size: int = 8
@dataclass(repr=False)
class DACParameters(BaseParameters):
"""Parameters for the digital-to-analog converter used to quantize the input signals
that are passed to the array.
Attributes:
model (DACModel): name of the model used to specify quantization behavior. This
must match the name of a child class of IDAC, other than "DAC"
bits (int): bit resolution of the digital input
input_bitslicing (bool): whether to bit slice the digital inputs to the MVM/VMM
and accumulate the results from the different input bit slices using
shift-and-add operations.
sign_bit (bool): whether the digital input is encoded using sign-magnitude
representation with a range that is symmetric around zero
slice_size (int): Default slice size for input bit slicing. Can be overridden
from within the individual cores
Raises:
ValueError: Raised if input bitslicing is enabled with incompatible options
"""
model: str = "IdealDAC"
bits: int = 0
input_bitslicing: bool = False
signed: bool = True
slice_size: int = 1
@property
def sign_bit(self):
return self.min < 0
def validate(self) -> None:
super().validate()
if self.input_bitslicing and self.bits == 0:
raise ValueError("Cannot use input bit slicing if inputs are not quantized")
@dataclass(repr=False) # Maybe rename this
class WeightErrorParameters(BaseParameters):
"""Parameters for the weight error model used.
Attributes:
enable (bool): Flag to enable adding weight errors
model (WeightErrorModel): Weight error model to use. This must match the name of
a child class of IDevice, other than "Device", "EmptyDevice", and
"GenericDevice"
magnitude (float): Standard deviation of the random conductance error that is
applied either as programming error or read noise when using one of the
generic device models. This is normalized either to either the maximum
device conductance (NormalIndependentDevice) or the target device
conductance (NormalProportionalDevice)
"""
enable: bool = False
model: str = "IdealDevice"
magnitude: float = 0
@dataclass(repr=False)
class ParasiticParameters(BaseParameters):
"""Parameters to describe behavior of parasitics.
Attributes:
enable (bool): Whether to enable parasitic resistance model. For bit sliced,
this indicates whether parasitics is enabled for ANY of the slices
Rp_row (float): Parasitic resistance of the row metallic interconnects
Rp_col (float): Parasitic resistince of the column metallic interconnects
gate_input (bool): If True, no parasitic voltage drops occur on the input side
regardless of Rp value. This implements the configuration where the input
row or column is connected to the gate of a transistor at every cell.
Because the transistor behaves as a switch, the input signal must be binary.
That means input bit slicing must be enabled
"""
enable: bool = False
Rp_row: float = 0
Rp_col: float = 0
gate_input: bool = False
def __post_init__(self):
return super().__post_init__()

xbar_parameters.py at commit 30f5ad1, under BSD-3-Clause · at the source

Overview

Authors: Samuel Liu^1,2, Vivian Rogers^1,2, Chen-Yu Hu³, Ming-Yuan Song³, Xinyu Bao³, Jean Anne C. Incorvia^1,2

ORCID iDs: Samuel Liu, Chen-Yu Hu, Xinyu Bao, Jean Anne C. Incorvia

Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA
Microelectronics Research Center, The University of Texas at Austin, Austin, TX, USA
Corporate Research, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan

Institutions: The University of Texas at Austin (United States); Taiwan Semiconductor Manufacturing Company (Taiwan) (Taiwan)

Journal: Science advances, volume 12, issue 35, article eaee6952

Dates: received 11 December 2025; accepted 20 July 2026; published online 28 August 2026; in print August 2026

Type: Research article · Language: English

License: CC BY-NC

Identifiers: DOI 10.1126/sciadv.aee6952 · PMID 42664328 · PMCID PMC13524016 · OpenAlex W7204601326

Open access: gold, a free copy (OpenAlex)

Status: code verified

Journal subjects: Physical and Materials Sciences, Engineering, Applied Sciences and Engineering

Topic: Magnetic properties of thin films (Atomic and Molecular Physics, and Optics, Physics and Astronomy), according to OpenAlex

Funding: Taiwan Semiconductor Manufacturing Corporation

Citations: not cited yet (Europe PMC); 97 references in the paper

Abstract

Analog crossbar arrays consisting of emerging memory devices can alleviate the computational strain required by vector matrix multiplications for neural network applications. The ability to produce spin orbit torque-magnetic random-access memory (SOT-MRAM) at wafer-scale positions SOT-MRAM as a strong memory candidate. In this work, we fabricate and measure 300 mm-compatible SOT-MRAM with 150% tunnel magnetoresistance (TMR) ratio, fast (2 ns) and low voltage (<1 V) operation, low energy dissipation (2 pJ), low write noise (0.1%), and low device-to-device variation of 10%. SOT-MRAM characteristics were shown to be effective for inference on calibrated models. The bi-stable anisotropy and stochastic switching of SOT-MRAM was leveraged for binary neural network training, able to reach ideal accuracy for a single device. Lastly, the devices were evaluated on probabilistic graph modeling and the interplay of TMR ratio and probability distribution is analyzed. Through these results, SOT-MRAM is shown to be a uniquely effective candidate for implementation of crossbar accelerators in memory- and energy-limited applications.

Reproduced under the paper's license (CC BY-NC), from the paper cited above.

Repositories

Its files are read in the Code ↔ Paper reader above, with 6 matches between paragraphs and lines of code.

Zenodo 19510921

License: CC-BY-4.0

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Size: 1 file

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Found in: “Data, code, and materials availability:”

Not found: README, license file, CITATION.cff, environment file, tests, continuous integration, documentation

Availability: 1 check, the latest on 27 September 2026: the link answers (HTTP 200)

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At the source: doi.org/10.5281/zenodo.19510921

Zenodo 19510936

License: CC-BY-4.0

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liukts/tsmc-sotmram-git

License: none: the authors keep all their rights

State: the link answers, verified on 27 September 2026

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Commit: eba84ec94894e843b3f1b897227d6cc6fb0f93f2, 1 April 2026

Languages: Python (25)

Size: 340 files, 25 scripts

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Holds: README

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Tools: NumPy (22 files), Matplotlib (14 files), PyTorch (8 files), SciPy (8 files), scikit-learn (2 files), seaborn (2 files), Keras (1 file), TensorFlow (1 file)

Availability: 1 check, the latest on 27 September 2026: the link answers

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26 files

pgm/pgm_main.py, Python, 106 lines
pgm/pgm_modules.py, Python, 83 lines
pgm/plot_errors.py, Python, 18 lines
pgm/plot_experror.py, Python, 16 lines
pgm/proc_errors.py, Python, 15 lines
pgm/pyspice_test.py, Python, 20 lines
stoch_train/acc_contour.py, Python, 43 lines
stoch_train/bnn_main.py, Python, 94 lines
stoch_train/dataloader.py, Python, 17 lines
stoch_train/optdigits_keras/keras_infmain.py, Python, 137 lines, 1 match
stoch_train/optdigits_keras/keras_infmodules.py, Python, 33 lines
stoch_train/optdigits_keras/save_map.py, Python, 23 lines
stoch_train/optdigits_keras/save_np.py, Python, 665 lines
stoch_train/optdigits_keras/save_optdigits.py, Python, 12 lines
stoch_train/plot_2nsswitch.py, Python, 62 lines
stoch_train/plot_accs.py, Python, 43 lines
stoch_train/plot_calculate_interp.py, Python, 73 lines
stoch_train/plot_d2d.py, Python, 32 lines
stoch_train/plot_mhloop.py, Python, 40 lines
stoch_train/plot_switchprob.py, Python, 58 lines
stoch_train/plot_varswitch.py, Python, 58 lines
stoch_train/plot_varswitch_log_combined.py, Python, 166 lines
stoch_train/plot_varswitch_power.py, Python, 248 lines, 1 match
stoch_train/torchinterp1d.py, Python, 168 lines
stoch_train/train_modules.py, Python, 335 lines, 1 match
README.md, Text, 1 line

At the source: github.com/liukts/tsmc-sotmram-git/tree/1.0

liukts/cross-sim-tsmc

License: BSD-3-Clause

State: the link answers, verified on 27 September 2026

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Commit: 30f5ad119b80280a27c3c17e91f65bbc0045b594, 8 April 2026

Languages: Python (99), Jupyter (3), MATLAB (1)

Size: 1,196 files, 103 scripts

Software Heritage: not archived

Found in: the Zenodo archive record

Holds: README, license file, environment (pyproject.toml), documentation, 3 notebooks

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Tools: NumPy (59 files), CuPy (23 files), SciPy (23 files), TensorFlow (14 files), Keras (11 files), Matplotlib (11 files), Pillow (5 files), OpenCV (4 files), PyTorch (1 file)

Availability: 1 check, the latest on 27 September 2026: the link answers

27 September 2026: the link answers

105 files

aaa_keras_trainer/convert_model.py, Python, 106 lines
aaa_keras_trainer/keras_infmain.py, Python, 273 lines
aaa_keras_trainer/keras_infmodules.py, Python, 33 lines
aaa_keras_trainer/plot_accs.py, Python, 32 lines
aaa_keras_trainer/plot_accs_log.py, Python, 30 lines
aaa_keras_trainer/plot_accs_new.py, Python, 32 lines
aaa_keras_trainer/plot_accs_newlog.py, Python, 40 lines
aaa_keras_trainer/plot_quant_log.py, Python, 30 lines
aaa_keras_trainer/proc_accs.py, Python, 26 lines
applications/dnn/dataset_loaders.py, Python, 406 lines
applications/dnn/inference/adc/calibrate_adc_mnist_cnn6v2.py, Python, 178 lines
applications/dnn/inference/adc/calibrate_adc_resnet50v15_1slice.py, Python, 187 lines
applications/dnn/inference/adc/calibrate_adc_resnet50v15_bitsliced.py, Python, 145 lines
applications/dnn/inference/adc/calibrate_adc_vgg19_1slice_percentile.py, Python, 118 lines
applications/dnn/inference/adc/calibrate_dac_mnist_cnn6v2.py, Python, 101 lines
applications/dnn/inference/adc/calibrate_dac_resnet50v15.py, Python, 102 lines
applications/dnn/inference/adc/calibrate_vgg19_dac_limits.py, Python, 101 lines
applications/dnn/inference/adc/mnist_cnn6_adc_limits.py, Python, 158 lines
applications/dnn/inference/adc/mnist_cnn6_dac_limits.py, Python, 101 lines
applications/dnn/inference/adc/resnet50_adc_limits_1slice.py, Python, 165 lines
applications/dnn/inference/adc/resnet50_adc_limits_1slice_ibit.py, Python, 118 lines
applications/dnn/inference/adc/resnet50_adc_limits_bitsliced.py, Python, 131 lines
applications/dnn/inference/adc/resnet50_dac_limits.py, Python, 102 lines
applications/dnn/inference/adc/vgg19_adc_limits_1slice_percentile.py, Python, 170 lines
applications/dnn/inference/adc/vgg19_dac_limits_optimizer.py, Python, 101 lines
applications/dnn/inference/helpers/custom_layers/clip_constraints.py, Python, 61 lines
applications/dnn/inference/helpers/custom_layers/layers_bnn.py, Python, 163 lines
applications/dnn/inference/helpers/imagenet_preprocess/MLPerf_cal_images.py, Python, 511 lines
applications/dnn/inference/helpers/imagenet_preprocess/generate_labels.py, Python, 58 lines
applications/dnn/inference/helpers/imagenet_preprocess/imagenet_path.py, Python, 9 lines
applications/dnn/inference/helpers/imagenet_preprocess/preprocess_MLPerfMobileNet.py, Python, 100 lines
applications/dnn/inference/helpers/imagenet_preprocess/preprocess_MLPerfRN50.py, Python, 99 lines
applications/dnn/inference/helpers/imagenet_preprocess/preprocess_keras.py, Python, 82 lines
applications/dnn/inference/helpers/imagenet_preprocess/preprocess_keras_inception.py, Python, 82 lines
applications/dnn/inference/helpers/imagenet_preprocess/preprocess_torchvision.py, Python, 85 lines
applications/dnn/inference/helpers/keras_model_builders/buildMobilenet_int8.py, Python, 383 lines
applications/dnn/inference/helpers/keras_model_builders/buildResnet50_int4.py, Python, 342 lines
applications/dnn/inference/helpers/keras_model_builders/buildResnet50v15.py, Python, 196 lines
applications/dnn/inference/helpers/qnn_adjustment.py, Python, 71 lines
applications/dnn/inference/inference_config.py, Python, 262 lines
applications/dnn/inference/interface/config_message.py, Python, 139 lines
applications/dnn/inference/interface/dnn_setup.py, Python, 919 lines
applications/dnn/inference/interface/inference_net.py, Python, 659 lines, 1 match
applications/dnn/inference/interface/keras_parser.py, Python, 635 lines
applications/dnn/inference/run_inference.py, Python, 269 lines
applications/dnn/inference/run_inference_errorloop.py, Python, 309 lines
applications/dnn/inference/run_inference_profiling.py, Python, 304 lines
applications/dsp/1d_dft_example.py, Python, 121 lines
applications/dsp/2d_dft_example.py, Python, 155 lines
applications/matlab/matlab_example.m, MATLAB, 103 lines
applications/mvm_params.py, Python, 281 lines
docs/sphinx/source/conf.py, Python, 50 lines
simulator/__init__.py, Python, 17 lines
simulator/algorithms/__init__.py, Python, 8 lines
simulator/algorithms/dnn/activate.py, Python, 153 lines
simulator/algorithms/dnn/convolution.py, Python, 395 lines
simulator/algorithms/dnn/dnn.py, Python, 1,277 lines
simulator/algorithms/dnn/dnn_util.py, Python, 171 lines
simulator/algorithms/dsp/dft.py, Python, 79 lines
simulator/backend/__init__.py, Python, 8 lines
simulator/backend/backend.py, Python, 105 lines
simulator/circuits/__init__.py, Python, 9 lines
simulator/circuits/adc/__init__.py, Python, 6 lines
simulator/circuits/adc/adc.py, Python, 92 lines
simulator/circuits/adc/cyclic_adc.py, Python, 159 lines
simulator/circuits/adc/iadc.py, Python, 222 lines
simulator/circuits/adc/pipeline_adc.py, Python, 175 lines
simulator/circuits/adc/quantizer_adc.py, Python, 92 lines
simulator/circuits/adc/ramp_adc.py, Python, 133 lines
simulator/circuits/adc/sar_adc.py, Python, 247 lines
simulator/circuits/array_simulator.py, Python, 346 lines
simulator/circuits/dac/__init__.py, Python, 6 lines
simulator/circuits/dac/dac.py, Python, 61 lines
simulator/circuits/dac/idac.py, Python, 58 lines
simulator/circuits/dac/quantizer_dac.py, Python, 132 lines
simulator/configs/__init__.py, Python, 10 lines
simulator/cores/__init__.py, Python, 45 lines
simulator/cores/analog_core.py, Python, 1,245 lines
simulator/cores/balanced_core.py, Python, 399 lines
simulator/cores/bitsliced_core.py, Python, 712 lines
simulator/cores/icore.py, Python, 85 lines
simulator/cores/numeric_core.py, Python, 314 lines
simulator/cores/offset_core.py, Python, 308 lines
simulator/cores/wrapper_core.py, Python, 179 lines
simulator/devices/__init__.py, Python, 8 lines
simulator/devices/custom/ECRAM_Chen.py, Python, 50 lines
simulator/devices/custom/PCM_Joshi.py, Python, 63 lines
simulator/devices/custom/RRAM_Milo.py, Python, 66 lines
simulator/devices/custom/RRAM_Sandia.py, Python, 50 lines
simulator/devices/custom/SONOS.py, Python, 269 lines
simulator/devices/custom/SOTMRAM_tsmc.py, Python, 54 lines
simulator/devices/device.py, Python, 141 lines
simulator/devices/generic_device.py, Python, 153 lines
simulator/devices/idevice.py, Python, 174 lines
simulator/parameters/__init__.py, Python, 21 lines
simulator/parameters/base_parameters.py, Python, 356 lines
simulator/parameters/core_parameters.py, Python, 256 lines
simulator/parameters/crosssim_parameters.py, Python, 30 lines
simulator/parameters/simulation_parameters.py, Python, 144 lines
simulator/parameters/xbar_parameters.py, Python, 453 lines, 2 matches
tutorial/tutorial_pt1.ipynb, Jupyter, 511 lines
tutorial/tutorial_pt2.ipynb, Jupyter, 605 lines
tutorial/tutorial_pt3.ipynb, Jupyter, 255 lines
LICENSE.md, License, 12 lines
readme.md, Text, 138 lines

At the source: github.com/liukts/cross-sim-tsmc/tree/1.0

The paper's code and data availability statement is in the Data section.

Tracing map

Proposed by the machine: these links were found in the paper and verified at the source, without human review. The map will receive a Zenodo DOI once one of the paper's authors has validated it with their ORCID.

What the map holds:

4 repositories of the authors' code, each at its verified commit, with its license and how the link was found in the paper;
128 scripts, each with its path and the digest of its content;
6 matches between paragraphs of the paper and lines of the code (method lexical-v1);
neither the text of the paper nor the code itself.

Its JSON (tracing-map.json) is deposited on Zenodo with its DOI once the map is validated.

Data

No dataset and no data link were found in the paper.

Data, code, and materials availability

All data and code needed to evaluate and reproduce the results in the paper are present in the paper, in the Supplementary Materials and in the Zenodo repositories (https://doi.org/10.5281/zenodo.19510921 and https://doi.org/10.5281/zenodo.19510936). This study did not generate new materials.

Reproduced under the paper's license (CC BY-NC), from the paper cited above.

Versions

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Version 1, 27 September 2026: the first record

Recorded: type, language, journal, volume, issue, pages, dates, 6 authors, 1 funder, 32 references.

Cite

This paper

Liu, S., Rogers, V., Hu, C.-Y., Song, M.-Y., Bao, X., & Incorvia, J. A. C. (2026). Wafer-scale SOT-MRAM for analog crossbar array applications. Science advances, 12(35), eaee6952. https://doi.org/10.1126/sciadv.aee6952

BibTeX

@article{liu2026wafer, author = {Liu, Samuel and Rogers, Vivian and Hu, Chen-Yu and Song, Ming-Yuan and Bao, Xinyu and Incorvia, Jean Anne C.}, title = {{Wafer-scale SOT-MRAM for analog crossbar array applications}}, journal = {Science advances}, year = {2026}, month = aug, volume = {12}, number = {35}, pages = {eaee6952}, publisher = {American Association for the Advancement of Science}, issn = {2375-2548}, doi = {10.1126/sciadv.aee6952}, url = {https://doi.org/10.1126/sciadv.aee6952}, pmid = {42664328}, pmcid = {PMC13524016} }

RIS

TY - JOUR AU - Liu, Samuel AU - Rogers, Vivian AU - Hu, Chen-Yu AU - Song, Ming-Yuan AU - Bao, Xinyu AU - Incorvia, Jean Anne C. TI - Wafer-scale SOT-MRAM for analog crossbar array applications T2 - Science advances J2 - Sci Adv PY - 2026 DA - 2026/08/28 VL - 12 IS - 35 SP - eaee6952 SN - 2375-2548 PB - American Association for the Advancement of Science DO - 10.1126/sciadv.aee6952 UR - https://doi.org/10.1126/sciadv.aee6952 LA - en ER -

CSL-JSON

{ "id": "10.1126/sciadv.aee6952", "type": "article-journal", "title": "Wafer-scale SOT-MRAM for analog crossbar array applications", "container-title": "Science advances", "author": [ { "family": "Liu", "given": "Samuel" }, { "family": "Rogers", "given": "Vivian" }, { "family": "Hu", "given": "Chen-Yu" }, { "family": "Song", "given": "Ming-Yuan" }, { "family": "Bao", "given": "Xinyu" }, { "family": "Incorvia", "given": "Jean Anne C." } ], "container-title-short": "Sci Adv", "volume": "12", "issue": "35", "page": "eaee6952", "DOI": "10.1126/sciadv.aee6952", "PMID": "42664328", "PMCID": "PMC13524016", "ISSN": "2375-2548", "publisher": "American Association for the Advancement of Science", "URL": "https://doi.org/10.1126/sciadv.aee6952", "language": "en", "issued": { "date-parts": [ [ 2026, 8, 28 ] ] } }

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Wafer-scale SOT-MRAM for analog crossbar array applications.

Code ↔ Paper

Paper

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Zenodo 19510921

Zenodo 19510936

liukts/tsmc-sotmram-git

liukts/cross-sim-tsmc

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