OSCR

A ferroelectric-ionic-trapping transistor for low power and secure neuromorphic computing.

Overview

Authors: Changhyeon Han1, Youngchan Cho2, Dongbin Kim1, Se-Hyun Hwang3, Minsuk Song1, Been Kwak1, David Radermacher2, Min Wook Kang4, Sangwan Kim4, Jangsaeng Kim3,5,6, Wonjun Shin2,4, Daewoong Kwon1
  1. Department of Electrical Engineering, Hanyang University, Seoul, Republic of Korea
  2. Department of Semiconductor Convergence Engineering, Sungkyunkwan University, Suwon, Republic of Korea
  3. Department of Semiconductor Engineering, Sogang University, Seoul, Republic of Korea
  4. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of Korea
  5. Department of Electronic Engineering, Sogang University, Seoul, Republic of Korea
  6. Department of System Semiconductor Engineering, Sogang University, Seoul, Republic of Korea
Institutions: Hanyang University (South Korea); Sungkyunkwan University (South Korea); Sogang University (South Korea)
Journal: Nature communications, volume 17, issue 1, article 7831
Dates: received 4 December 2025; accepted 28 April 2026; published online 29 May 2026
Type: Research article · Language: English
License: CC BY
Identifiers: DOI 10.1038/s41467-026-72971-y · PMID 42215429 · PMCID PMC13439170 · OpenAlex W7162768908
Open access: gold, a free copy (OpenAlex)
Status: code on request
Methods: Statistics, Spectral & time-frequency
Keywords: Electrical and electronic engineering, Electronic devices
Topic: Ferroelectric and Negative Capacitance Devices (Electrical and Electronic Engineering, Engineering), according to OpenAlex
Funding: National Research Foundation of Korea (NRF) (RS-2023-00260527, RS-2025-23323231)
Citations: not cited yet (Europe PMC); 60 references in the paper

Abstract

The convergence of artificial intelligence and pervasive data analytics has created an urgent demand for energy-efficient and secure computing hardware. Neuromorphic synaptic devices emulate the human brain with high parallelism and 3D connectivity to reduce power consumption, yet they lack intrinsic mechanisms to protect stored information from malicious read-out. Here we report a ferroelectric–ionic–trapping field-effect transistor (FITFET) that integrates ferroelectric polarization, oxygen-vacancy migration, and charge trapping to enable both synaptic and secure functionality. The FITFET operates in two programmable regimes: a plain mode combining fast, low-power ferroelectric switching with analog weight modulation, and a secure mode in which the memory window collapses under specific read biases, concealing stored states and suppressing read attacks. This reversible, voltage-controlled transition provides a hardware-native data protection mechanism. Multiscale analyses demonstrate reliable switching between learning and concealment, while system-level simulations show reduced model inversion attacks with minimal accuracy loss.

Reproduced under the paper's license (CC BY), from the paper cited above.

Code

The paper says that its authors' code is available on request: it was not published with the paper, so there is nothing to verify.

Code availability

All relevant codes used for the simulation are available in the article and Supplementary Information. All other codes are available from the corresponding authors on request.

Reproduced under the paper's license (CC BY), from the paper cited above.

Tracing map

A tracing map links a paper to the code its authors published: this paper has none (its code is available on request), so it has no map.

Data

No dataset and no data link were found in the paper.

Data availability

The data that support the findings of this study are available in the Supporting Information of this article. The data generated in this study are provided in Source Data files. All other data is available from the corresponding author upon request. Source data are provided with this paper.

Reproduced under the paper's license (CC BY), from the paper cited above.

Versions

The history of this record: each version stored by the harvester or made by a correction of its authors or of the maintainers of its code, and what changed in its facts. The texts of the paper (its abstract, its availability statements) are not part of it; versions that changed only those are not listed.

Version 1, 28 September 2026: the first record

Recorded: type, language, journal, volume, issue, pages, dates, 12 authors, 2 keywords, 1 funder, 29 references.

Cite

This paper

Han, C., Cho, Y., Kim, D., Hwang, S.-H., Song, M., Kwak, B., Radermacher, D., Kang, M. W., Kim, S., Kim, J., Shin, W., & Kwon, D. (2026). A ferroelectric-ionic-trapping transistor for low power and secure neuromorphic computing. Nature communications, 17(1), 7831. https://doi.org/10.1038/s41467-026-72971-y

BibTeX

@article{han2026ferroelectric,
author = {Han, Changhyeon and Cho, Youngchan and Kim, Dongbin and Hwang, Se-Hyun and Song, Minsuk and Kwak, Been and Radermacher, David and Kang, Min Wook and Kim, Sangwan and Kim, Jangsaeng and Shin, Wonjun and Kwon, Daewoong},
title = {{A ferroelectric-ionic-trapping transistor for low power and secure neuromorphic computing}},
journal = {Nature communications},
year = {2026},
month = may,
volume = {17},
number = {1},
pages = {7831},
publisher = {Nature Publishing Group},
issn = {2041-1723},
doi = {10.1038/s41467-026-72971-y},
url = {https://doi.org/10.1038/s41467-026-72971-y},
pmid = {42215429},
pmcid = {PMC13439170}
}

RIS

TY - JOUR
AU - Han, Changhyeon
AU - Cho, Youngchan
AU - Kim, Dongbin
AU - Hwang, Se-Hyun
AU - Song, Minsuk
AU - Kwak, Been
AU - Radermacher, David
AU - Kang, Min Wook
AU - Kim, Sangwan
AU - Kim, Jangsaeng
AU - Shin, Wonjun
AU - Kwon, Daewoong
TI - A ferroelectric-ionic-trapping transistor for low power and secure neuromorphic computing
T2 - Nature communications
J2 - Nat Commun
PY - 2026
DA - 2026/05/29
VL - 17
IS - 1
SP - 7831
SN - 2041-1723
PB - Nature Publishing Group
DO - 10.1038/s41467-026-72971-y
UR - https://doi.org/10.1038/s41467-026-72971-y
LA - en
ER -

CSL-JSON

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